1. Field of the Invention
This invention relates generally to integrated circuits and more particularly concerns the use of integrated logic circuitry that can be implemented in the efficient testing of integrated circuit designs.
2. Description of the Related Art
Electronic devices, such as computer chips, can include thousands upon thousands of logic circuits. To ensure that the logic circuits are operating correctly before they are put to use, these circuits are tested to verify wiring and timing integrity. To facilitate this testing, during fabrication flip-flops are configured with multiplexers to form scan-flops. Usually, many scan flops are linked together throughout the IC design to form a chain of scan flops. A scan flop chain, therefore, will enable operation in both a test mode and a functional normal mode.
As is well known, there is often a need to have control over the clock signal that is communicated to the individual scan flops. To achieve this control, it is known to introduce some type of gating logic that is external to the individual scan flops. By introducing external clock gating logic, better control is provided as to when the scan flops change state. When a larger number of scan flops are used in a particular design, there is also a need to perform buffering on the clock lines. The buffering circuitry is generally designed to be well balanced such that all of the scan flops will still clock at about the same time. However, if both clock gating and clock buffering is desired, the clock line will have both clock gating and buffering circuitry.
To accurately test the timing parameters of the circuit design, delays introduced by the clock gating and the clock buffering will have to be accounted for during the delay calculation. This is required so that all of the scan flops will clock at about the same time. Unfortunately, a difficulty can arise in determining whether the clock buffering should be performed before or after the gating logic. In many cases, the introduction of clock buffering logic can complicate timing calculations so much that standard analysis tools find it difficult to accurately test data setup and hold times relative to clock. An exemplary commercially available analysis tool is called Sunrise.TM., and is available from Synopsys, of Mountain View, Calif.
Known prior art designs that find the need for gated clocks, generally utilize external clock gating circuitry. For instance, U.S. Pat. No. 5,598,112, which is hereby incorporated by reference, describes a circuit for generating a demand-based gated clock. As taught therein, an external circuit 50 is used to generate a gated clock to the register 10. The external gating circuitry will therefore have to be accounted for during the timing analysis of the IC design. In some cases, when the external gating logic circuitry grows relatively large, typical software analysis tools will fail to accurately generate a testing result. In such cases, designers are often called upon to perform very time consuming manual delay calculations. For very large designs, manual calculations are not only time consuming, but they can be prone to human error. Any degree of introduced error will therefore have the disadvantage of decreasing the reliability of the testing.
In view of the foregoing, there is a need for scan flop circuitry that enables clock gating, but does not introduce additional external logic that can complicate clock buffering or other automated testing operations.